1. Field of the Invention
The present invention relates to a vertical deflection circuit with an improved linearity.
2. Description of the Prior Art
In the vertical deflection circuit, it is important to maintain a superior linearity of deflection. For this purpose, a resistor with a low resistance value is connected in series with a vertical deflection coil, and a saw-tooth wave voltage generated across this low-value resistor is negatively fed back to a driving stage for driving a vertical output stage.
Such a vertical deflection circuit is disclosed, for instance, in Japanese Patent Publication No. 37,732/76. In this well-known vertical deflection circuit, it is impossible to obtain satisfactory linearity characteristics unless a trapezoidal wave voltage supplied to the driving stage is stabilized on the one hand and the variation in the amplification degree of transistors making up the driving stage and the vertical output stage is reduced on the other hand.
Another well-known type of vertical deflection circuit is such that a saw-tooth wave voltage is applied to the driving stage, and another saw-tooth wave voltage generated across the low-value resistor in series with the vertical deflection coil is negatively fed back to the driving stage, and these two saw-tooth voltage are used to produce a trapezoidal wave voltage at the output of the driving stage, thus improving the stability. In this prior vertical deflection circuit, however, the trapezoidal wave voltage produced at the output of the driving stage is not sufficient to directly drive the vertical output stage including two NPN output transistors connected in single-ended push-pull. If the vertical output stage is directly driven, the linearity is deteriorated for the reason mentioned below.
The two NPN output transistors are arranged in such a manner that the collector-emitter circuit thereof is connected in series between the positive pole of a DC power supply and the earth, and the NPN output transistor on the positive pole side conducts in the former half of the vertical scanning period and acts as an emitter follower, while it is cut off in the latter half of the vertical scanning period. The NPN output transistor on the earth side, on the other hand, conducts during the vertical scanning period and acts as an emitter-grounded transistor. In the former half of the vertical scanning period, all the emitter current of the NPN output transistor on the positive pole side flows through the vertical deflection coil, and therefore the NPN output transistor on the positive pole side fails to make up a collector load of the earth-side NPN output transistor. Namely, the collector load of the earth-side NPN output transistor is formed by a base bias circuit of the NPN output transistor on the positive pole side during the former half of the vertical scanning period, while it is formed by a series circuit including the vertical deflection coil and the low-value resistor in the latter half of the vertical scanning period. The ratio of change in this collector load is 1/10 or less than 1/10. Therefore, the mutual conductance, that is the ratio between the input voltage applied to the driving stage and the output current produced from the output stage assumes, in the latter half of the vertical scanning period becomes, several percents of the value for the former half thereof. As a result, the lower part of the reproduced picture in TV is "crimped". In other words, the amplification degree of the vertical output stage in the former half of the vertical scanning period is so different from that in the latter half thereof that the linearity of vertical deflection signal is deteriorated.